DS1678S/T&R【PDF 20/25 页】IC RECORDER REALTIME EVENT 8SOIC

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DS1678 Real-Time Event Recorder

4 of 25

Note 1:

Limits at -40

C are guaranteed by design and not production tested.

Note 2:

All voltages referenced to ground.

Note 3:

After this period, the first clock pulse is generated.

Note 4:

A device must initially provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of the falling edge

of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

Note 5:

A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is

automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL

line is released.

Note 6:

CB—Total capacitance of one bus line in pF.

Note 7:

tR and tF are measured with a 1.7k pullup resistor, 200pF pullup capacitor, 1.7k pulldown resistor, and 5pF

pulldown capacitor.

2C COMMUNICATION TIMING DIAGRAM

SU:STO

HD:STA

t SU:STA

SU:DAT

tHIGH

tLOW

tHD:STA

SCL

START

SDA

STOP

tBUF

REPEATED

START

tHD:DAT

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